Study Process

MIET and Cadence specialists have developed a complete syllabus, which will be available to other Cadence University Campus Program participants. As of September 2003, two groups totaling 50 students are being trained according to this syllabus in MIET. After graduating the student’s will obtain a Master’s degree. Students are taught by MIET lecturers as well as by industry specialists from leading companies involved in integrated microelectronic circuit design.

Students of the Institute study 25 technical courses supported with appropriate laboratory projects and practical training. In addition, students study English and intern at IC design companies such as Angstrem, Intel, Motorola, and Unique IC.

A typical student has a Bachelor’s degree in engineering and has graduated from the 4th course of MIET. Students of other institutes may also be admitted if they studied according to similar requirements. To enter the Institute, students of any MIET department must pass a written test, submit data on their progress in their main course of study, and include information on their work (practice) at electronic companies.

Special Courses to be studied at the DSD Institute

1.	IC Components and Their Models
2.	Introduction into CADENCE
3.	Current and Advanced VLSI Technologies
4.	Standard Cell Design. Introduction into Verilog
5.	CMIS LSI Electrical Design Features
6.	Low Frequency Analog IC Design
7.	Digital IC Design.
8.	Sensors
9.	Analog IC Layout Design
10.	Special Chapters of Analog IC Design
11.	Filters and Frequency Synthesis of Circuits
12.	Wideband and RF circuits
13.	Introduction into SHF Facilities
14	AIC Standard Cell Design
15	Introduction into Discrete and Analog Circuits
16	VLSI-On-Programmable-Chip Design
17	ADC, DAC
18	VLSI Testing and Control
19	System-On-Chip Design
20.	Sun-Solaris/Unix Operational Systems
21	Programming Languages Skill, Perl.
22	Analytical Functions and Their Applications
23	Cadence Database
24	Technical Documents

MASTER’S DEGREE COURSE GENERAL CURRICULUM

Device and sYstem design INSTITUTE

PROGRAM OF 2nd DSD GROUP (September 2003)

4 term 2004/2005 07. 02-25.06 8+8+4 hours	Practice: 2 month	Engl. 4-hr seminar, credit	DSD 17. ADC, DAC 2 hours (1-hr lecture, 1-hr labs) credit	DSD 18. VLSI testing and control. 3 hours (2-hr lecture, 1-hr labs) credit	DSD 19 System-on-chip design. 3 hours (1-hr lecture, 2-hr labs) credit	20 Preparation of Master’s thesis. 8 hours. (April. March)
3 term 2004/2005 01.09-29.01 17+3 hours	Practice: 3 day a week	Engl. 3-hr seminar, credit	DSD10 Special chapters of AIC design. 2-hr lecture examination.	DSD 11 Pll, CDR and Freq synthesis of circuits 2.5 hours (1.5 hr lercure, 1-hr labs) examination	DSD 12 Wideband and RF design 1.5 hours lecture, examination	DSD 13 Introduction into SHF facilities. 1-hr lecture, credit	DSD 14 AIC standard cell design 3-hours (1-hr lecture, 2-hr labs)	DSD 15 Introduction into Analog Sampled-Data Circuits Design. 3 hours (2-hr lecture, 1-hr labs) Project, examination	DSD 16 VLSI-on-programmable-chip design. 4hours (2-hr lecture, 2-hr labs) credit
2 term 2003/2004 09.02-26.06 18 +1 hours	Practice: 3 day a week	Engl. 2+1-hr seminar, credit	Philosophy 2-hr lect., examination	DSD 6 Low freq analog circuit design 5 hours (3-hr lecture, 2-hr labs) examination	DSD 7 Digital IC design 3 hours (1-hr lecture, 2-hr labs). VERILOG. 2 hours labs, credit.	DSD 8 Sensors. 1-h lect., credit	DSD 9 AIC layout design 4 hours (2-hr lecture, 2-hr labs) credit	DSD 23 Analytical functions and their applications 1 hour lectures credit	DSD24 Cadence-Database, programming languages. 1.5 hours (1 hr lecture, 0.5-hr labs), credit	DSD25-Technical documents 0.5 hour seminar, (home work) credit
1 term 2003/2004 01.09-28.01 17 hours	Practice: 3 day a week	Engl. 2-hr seminar, credit	Philosophy 2-hr lect., credit	DSD 1 IC components and their models. 2.5 hours (2h lect, 0.5h labs) examination	DSD 2 Introduction into CADENCE. 3 hours (1-hr lecture, 2-hr labs) credit	DSD 3 Current and advanced VLSI technologies 2 hours (2-hr lecture) credit	DSD 4 Standard cell design. Introduction into VERILOG. 4 hours (2-hr lecture, 2-hr labs). examination	DSD 5 CMIS LSI electrical design features 2.5 hours (0.5-hr lecture, 2-hr seminar) credit	DSD21 Operational system Sun-Solaris/Unix 1 hour labs credit	DSD22 Skill, Perl. 2 hours 0.5 hr lecture, 1.5 hr labs credit

APPROXIMATE THEMES FOR MASTER’S THESES.

Analog IC parameter extraction: buses over the resistor, inductances, capacitors.

Centroids: comparative analysis of designs.

Library development for a specific circuit device (controller).

Automated library element creation in Cadence CAD system.

Delay elements. Circuit engineering, layout.

Design Rule Check.

OA Debugger development using Open Access database.

Secondary electric power supply sources, voltage stabilizers.

Operational amplifiers, classification methods, main parameters, calculation methods.

Studying AB class operational amplifier.

Studying A class operational amplifier with a dynamic mode current.

Developing Verilog code of port I2S interface with augmented functionality for the МР3-type.

Quartz generator. Studying implementation methods. Parallel and series resonance analysis.

Studying ESD protection, element matching and thyristor ignition. Layout versions.

Studying methods of improving temperature stability accuracy of reference voltage sources.

Topological methods of providing reliability of analog and mixed CMOS ICs.

Studying the efficiency of various models of internal layout representation to fulfill various operations with the layout (AND, OR, SIZE), while carrying out layout verification operations.